Reliably producing submicron and smaller features is one of the key technologies for the next generation of very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as the miniaturization of circuit technology is pressed, the shrinking dimensions of interconnects in VLSI and ULSI technology have placed additional demands on the processing capabilities. The multilevel interconnects that lie at the heart of this technology require precise processing of high aspect ratio features, such as vias and other interconnects. Reliable formation of these interconnects is very important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates.
As circuit densities increase for next generation devices, the widths of interconnects, such as junctions, vias, trenches, contacts, gate structures and other features, as well as the dielectric materials therebetween, decrease to 45 nm and 32 nm dimensions and beyond, whereas the thickness of the epitaxial layers remain substantially constant, with the result of increasing the aspect ratios of the features. Many traditional deposition processes have difficulty filling narrow vertical structures with small width where the aspect ratio exceeds 10:1. For example, a silicon layer deposited using a deposition process often suffer from poor step coverage, overhang, seams, and voids formed within the via or trench when the via is less than 30 nm or having a high aspect ratio. Insufficient deposition on the bottom and sidewall of the vias or trenches can also result in deposition discontinuity, thereby leading to device shorting or poor interconnection formation.
Conventionally, a gap-fill deposition process may include both deposition and etching steps so as to fill a structure with high aspect ratios without early close-up of the openings during the deposition process. However, these processes often require high process temperature, which may adversely create processes to the device structures formed on the substrate with low thermal budget. Furthermore, high temperature process for a gap-fill process often requires high manufacturing cost and longer overall process time.
Therefore, there is a great amount of ongoing effort being directed at the formation of substantially void-free, seam-free and conformal submicron features having high aspect ratios or small dimensions.